This invention relates to a thin film transistor used in an electronic instrument, such as a display, a sensor or a printing device, or a semiconductor device, such as a memory or a CPU, and a method for fabricating the same.
Hitherto, a technology for fabricating a thin film transistor (a TFT, hereinafter) formed of hydrogenated amorphous Si (a-Si:H) or polycrystalline Si has been developed and put to practical use as a representative technology for fabricating the TFT on an insulating substrate such as a glass substrate.
In the technology for fabricating the hydrogenated amorphous Si (a-Si:H)TFT, the maximum temperature in the fabrication process is about 300xc2x0 C., and the carrier mobility of about 1 cm2/Vsec is realized.
Accordingly, the TFT fabricated by using the aforementioned technology is used as a switching transistor for each pixel in an active matrix liquid crystal display (an AM-LCD, hereinafter), and in this case, the pixel-TFT is driven by a driver circuit (an IC or a LSI fabricated on a Si substrate formed of a single crystal).
Moreover, since each pixel is provided with the switching TFT in the AM-LCD, a cross talk is reduced. And an image with an excellent quality can be obtained as compared with a passive matrix LCD.
On the other hand, in the technology of the TFT formed of polycrystalline Si, the high carrier mobility of 30 to 100 cm2/Vsec can be realized by using the high temperature fabrication process which is similar to that of a LSI based on a SiO2 substrate and conducted in the maximum temperature of about 1000xc2x0 C.
Accordingly, if the aforementioned technology is applied to the LCD, the pixel-TFTs and the peripheral driving circuits for the pixel-TFTs can be formed on the same glass substrate.
Moreover, according to the conventional technology, due to recent tendency that the LCD is compact and the resolution of the picture thereof is improved, it becomes extremely difficult to join the ICs serving as the peripheral drivers with the AM-LCD substrate by means of TAB connection or wire bounding because of a narrow pitch of joining. However, this difficulty can be overcome by means of the TFTs formed of polycrystalline Si, fabrication cost can be cut down, and products can be small sized.
However, according to the technology of the TFT formed of polycrystalline Si, since the fabrication process is carried out in a high temperature, glass with low softening temperature and with a low cost which has been used in a fabrication process of the TFT formed of hydrogenated amorphous Si cannot be used.
Accordingly, in order to reduce the maximum temperature in the fabrication process of the TFT formed of polycrystalline Si, a method for forming a polycrystalline Si layer in a low temperature region by means of laser crystallization technology is being studied and developed.
In general, a laser pulse irradiation apparatus realizes a crystallization technology by means of laser irradiation with a structure shown in FIG. 1.
A laser light which functions as an energy beam and is emitted from a pulse laser light source passes through an optical path regulated by optics, such as mirrors and a beam homogenizer for spatially homogenizing a light intensity, and reaches a Si layer formed on a glass substrate 5.
Since a region irradiated by the laser light is far smaller than the glass substrate in most cases, the laser light irradiates a desired position by displacing the glass substrate by means of a x-y stage. A method that the aforementioned optics are displaced without using the x-y stage or both the optics and the stage are displaced is adopted also.
The polycrystalline Si layer formed by laser irradiation is used for a TFT as shown in FIG. 2.
In the TFT shown in FIG. 2, a channel region 7, a source region 8, a drain region 9 and a lightly doped drain (a LDD, hereinafter region 14 are formed on a glass substrate 5 covered with a substrate-coating layer 19, and a gate insulating layer 12 and a gate electrode 10 are formed thereon. Moreover, a SiO2 layer 4 is deposited, and a metallic layer 11 is formed in a contact hole.
The LDD regions 14 which are provided for the TFT and serve as offset gate regions suppress an off-leak current caused by trap levels which are generated around grain boundaries with high density in the polycrystalline Si semiconductor.
However, according to the aforementioned method for forming a polycrystalline Si layer by means of laser irradiation, grain sizes widely vary in a range extending from several nm to several xcexcm in accordance with an intensity of a laser light, a width of a pulse and the number of the pulses, and it is difficult to uniformly grow crystal grains with a desired grain size at a desired position. Especially, in crystallization by means of an excimer laser, since nucleation occurs in an extremely short time in the order of nano second in the processes of a laser light absorption and recrystallization of the Si layer, it is very difficult to uniformly grow the crystal grains at a desired position.
The engineer of the semiconductor device faces the aforementioned difficulties in case that he tries to grow a polycrystalline Si layer in a solid phase or to directly deposit the same on a glass substrate as well as in case that he tries to form the same by means of laser crystallization technology.
As mentioned in the above, since the states of the grain boundaries are not uniform in the conventional TFTs, the off-leak currents fluctuate, and this difficulty is not overcome even if the LDD regions are formed at both the side ends of the channel region, hence the off-leak current cannot be precisely reduced as a result.
A semiconductor IC comprising the TFT which reduces the off-leak current by means of low density off set gate regions (LDD regions) formed in the channel region is disclosed in Japanese Patent 2525707 as a technology for overcoming the aforementioned difficulty.
However, since the state of the grain boundaries of the TFT is not uniform as mentioned in the above, the off-leak current cannot be precisely reduced. Especially, in the step of crystallizing the Si layer by means of the excimer laser irradiation, generation of the crystalline nucleuses cannot be controlled, and the aforementioned difficulty cannot be completely overcome.
Moreover, in a semiconductor device for overcoming the aforementioned difficulty disclosed in Japanese Patent Application Laid-open No. 9-293870, an electrical conductive layer with a high heat conductance is inserted between a glass substrate and an alkali metallic ion-obstructing layer.
In the aforementioned technology, melted Si is almost uniformly cooled and solidified, and a polycrystalline Si layer composed of crystal grains with a particular orientation can be obtained. Although a TFT with the high carrier mobility can be obtained by the aforementioned technology, an off-leak current cannot be precisely reduced, and location of nucleation cannot be precisely controlled, hence the aforementioned problem cannot be completely solved.
In the aforementioned TFT disclosed in Japanese Patent Application Laid-open No. 9-293870, the structure of a lamination of the TFT is described as an electrical conductive layer with a high heat conductance/a gate electrode/an insulating layer/a Si layer, which is radically different from a structure of an embodiment of the present invention (an electrical conductive layer with a high heat conductance/an insulating layer/a Si layer/an insulating layer/a gate electrode). Accordingly, it can be concluded that the TFT according to the present invention is different from that according to Japanese Patent Application Laid-open No. 9-293870 in their objects and effects.
Accordingly, it is an object of the invention to provide a thin film transistor and a method for fabricating the same, in which an off-leak current caused by trap levels formed around grain boundaries is radically reduced by eliminating the grain boundaries in accordance with a single crystallization of Si layers.
It is a further object of the invention to provide a thin film transistor and a method for fabricating the same, in which an off-leak current and the fluctuation thereof are precisely reduced by forming size-controlled crystal grains at desired locations.
According to the first feature of the invention, a thin film transistor comprises:
a cooling layer formed on a substrate,
an insulating layer formed on the cooling layer, a heat conductivity of the cooling layer being higher than that of the insulating layer, and
a semiconductor layer which is formed on the insulating layer and comprises a drain region, a channel region and a source region,
wherein the cooling layer is locally close to at least one of the drain region, the channel region and the source region.
According to the aforementioned structure, in case that the Si layer formed on the insulating layer is irradiated with an excimer laser beam to form a crystalline Si layer, crystalline nucleuses are formed on a portion of an active region (the drain, channel and source regions) which is locally close to the cooling layer, and crystallization starts from the crystalline nucleuses towards regions where melted Si layer is cooled a certain time later.
Accordingly, a Si layer formed of a single crystal or size-controlled crystal grains can be made up by epitaxially growing a Si layer around the crystalline nucleuses, and the TFT which radically reduces an off-leak current caused by trap levels generated around grain boundaries can be fabricated by means of the aforementioned Si layer, hence the off-leak current of the TFT can be precisely reduced.
In the structure according to various embodiments of the invention, either of at least one of the drain, channel and source regions or the cooling layer closely approaches the remainder.
As mentioned in the above, since the engineer of the semiconductor device is given a wide range of choice in designing the structure of the cooling layer and an active region (the drain, channel and source regions) of a semiconductor device, degree of freedom in the design is increased, and the optimum design can be performed.
In the structure according to another embodiment of the invention, a gate electrode is formed on the channel region, and the drain region closely approaches the cooling layer.
Accordingly, since a single crystal region or an size-controlled crystal grain region can be formed in the neighborhood of the drain region, that is to say, in the channel region, the off-leak current can be effectively reduced.
Explaining concretely, the off-leak current in the drain region peculiar to polycrystalline Si can be reduced by designing the TFT so that a Si layer formed of a single crystal is made up in the neighborhood of the drain region.
In the structure according to another embodiment of the invention, the cooling layer of the TFT has a shadowing property.
According to the aforementioned structure, photo-carriers can be prevented from being generated in condition an external light illuminates the TFT, and thereby a wrong operation can be avoided. The aforementioned characteristic is appreciated in a LCD used in a liquid crystal projector, which is exposed to a strong light, and especially in the TFT for driving a pixel in a liquid crystal.
According to the second feature of the invention, a method for fabricating a TFT comprises the steps of
forming a cooling layer with a high heat conductivity on a substrate,
forming an insulating layer with a lower heat conductivity than that of the cooling layer on the cooling layer,
locally thinning the insulating layer,
forming a semiconductor layer on the locally thinned insulating layer, and
irradiating the locally thinned insulating layer with an energy beam.
A method for fabricating a TET according to one embodiment of the invention, comprises the steps of:
forming a semiconductor layer on a substrate,
forming a cooling layer with a higher heat conductivity than that of the semiconductor layer on the semiconductor layer,
patterning the cooling layer,
irradiating the semiconductor layer and the cooling layer with an energy beam, and
removing at least a portion of the cooling layer.
As mentioned in the above, a Si layer formed of a single crystal region or a size-controlled crystal grain region can be made up by forming a cooling layer on the Si layer and by patterning the same, and thereby the off-leak current can be reduced radically and precisely.